Ekansh Gupta
Ekansh Gupta
@YashKumarVerma, what is the status.? Can you let me know, what I have to do?
We are already working on adding Verilog, Adding VHDL wouldn't be a very big deal.
Firstly we need to add a page explaining VHDL
Looks pretty good! Nice effort!
Created Verilog Informative Page. Operators.png yet to be merged with the master. Kindly adjust its order in the Interactive book
https://github.com/CircuitVerse/Interactive-Book/issues/368
@mahmodHammad Can I resolve everything by 29th? I will attach everything here. Something's coming up tomorrow. Sorry for the delay
Will be used in a later PR. Please merge @Shivansh2407
Are you comfortable writing an simulating of ARM x86? Can you write some organic content on FPGAs?
If you want any help, let me know