Aliaksei Chapyzhenka
Aliaksei Chapyzhenka
https://travis-ci.org/sifive/duh/jobs/525755599
https://travis-ci.org/sifive/duh/jobs/525755598
- [x] Export Verilog blackbox [ #4 ] - [x] Import Verilog Pinlist - [ ] Import Verilog Parameters - [ ] Export Verilog composition
[Wiki](https://en.wikipedia.org/wiki/SystemRDL) [Spec](https://accellera.org/images/downloads/standards/systemrdl/SystemRDL_2.0_Jan2018.pdf) https://github.com/SystemRDL https://github.com/drom/tree-sitter-systemrdl SystemRDL uses Perl as preprocessor language. - [ ] Import SystemRDL