Aliaksei Chapyzhenka issues

Results 269 issues of


                                            Aliaksei Chapyzhenka

cascading attributes: memoryMap -> register -> field

access?

CLIi to validate parameters against component parameter schema

enhancement

Travis CI failing on Windows

https://travis-ci.org/sifive/duh/jobs/525755599

Travis CI failing on OSX

https://travis-ci.org/sifive/duh/jobs/525755598

Verilog integration

- [x] Export Verilog blackbox [ #4 ] - [x] Import Verilog Pinlist - [ ] Import Verilog Parameters - [ ] Export Verilog composition

import

export

[Wiki](https://en.wikipedia.org/wiki/SystemRDL) [Spec](https://accellera.org/images/downloads/standards/systemrdl/SystemRDL_2.0_Jan2018.pdf) https://github.com/SystemRDL https://github.com/drom/tree-sitter-systemrdl SystemRDL uses Perl as preprocessor language. - [ ] Import SystemRDL

registers

import

export

display Verilator code coverage report

add clock / reset definition

enhancement

user parameter schema

enhancement

support logicalTieOff in portMap

enhancement