Dong Wang

Results 7 issues of Dong Wang

I am using vitis version 2021.2 with the zcu102_base_dfx platform. In the generated summary file, the clock frequency was not correctly recognized from the hardware, for example, the default clock...

I am upgrading from 2020.1 to 2021.1, but I have found inconsistent behavior of the xrt on the zcu102 edge device. I am testing with parallel kernels as a producer...

Hi, I am working on the ZC706 board with MIG (PL-DDR) enabled in a custom vitis platform. When using clEnqueueMigrateMemObjects to write buffers, the content of the buffers on the...

Hi, I am runing vitis acceleration applications on a ZCU102 boards, It was found that the operation clsetKernelArgs has very long latency. The following pic are from vitis analyzer. When...

Hi, I am trying to create large buffers larger than 130M, but the driver failed with the following errors: ![Image](https://github.com/user-attachments/assets/d1492f23-d384-4dbc-80af-1a144864835b) I have set CMA=512M as follow, still can not work:...

I am using the U55c board and vitis 2022.1, I have found that the kernel launching latency is very large (50us~100us), this may cause a big differnece when using the...