Mohamed Gaber
Mohamed Gaber
You could decrease the max capacitance violations by setting a more aggressive fanout constraint early on (during synthesis): for example, set `MAX_FANOUT_CONSTRAINT` to `6` instead of the default `10`. This...
You can decrease it further. But you have hold violations in the fast corner which is a much bigger problem.
Still happening here.
Argh, victim of the new release. Sorry about that! You can roll back to working version temporarily as follows: 
We've gone ahead and made the Colab use Version 2.1 by default until we figure out what's wrong with 2.2
Sorry for the extremely late reply. There's not much we can do about this… except for maybe a lib to verilog converter of some kind.
We'll have to go through all the designs anyway for #523 so this can be lumped in with that.
Acknowledged- will decide on the proper course of action since OpenLane 1's whole raison d'être now is that we don't change things too much We'll definitely do that for 2...
Yeah, we don't unless we have a very good reason
@pramchan Oh, sorry for the late repsonse. If you're stuck still, Yosys has a number of new arguments to `read_liberty` which you can use `-ignore_miss_func` to work around this specific...