dmukherj09

Hi @hughes-c, thanks for the reply. Can you help me to figure out how to flush the cache lines one by one for now?

Thank you, I'll check the links out

That is a great suggestion, thank you!!

Hi I think so too that the requests are getting splitted which is the reason for more number of requests to the DRAM simulator, but the prosperoCPU log says --...

Okay so I confirmed your logic, and seems like yes, there's a increase in the number of memory requests because of the splitting of the requests depending upon the request...

I verified that the requests were being split by doing an experiment by sweeping the request size and checking the resultant requests in the main memory model. Whenever the requests...

The SST-Core and the SST-Element version is 12.1.0 The prospero input is 49M memory requests from a file which has following pattern (it is spec2016 benchmark #500)-- Format is --...

The SDL File is -- ``` import sst from mhlib import componentlist statFile = "stats_cramsim_big_latency.csv" statLevel = 16 def read_arguments(): boolUseDefaultConfig = True def setup_config_params(): l_params = {} if g_boolUseDefaultConfig:...

The above SDL is file is mainly following the testBackendCramsim in the memHierarchy/tests/ directory and replacing the default CPU model with a prospero model

Hi @plavin I have updated the code above