dlushni-pw

UART Mode Register XUARTPS_MR_OFFSET at offset 0x4 has a 2-bit field to set the desired stop mode (check XUARTPS_MR_STOPMODE_2_BIT 0x80, XUARTPS_MR_STOPMODE_1_5_BIT 0x40). This 2-bit bitfield includes consecutive bits 7, and...

That is correct, and the XUARTPS_MR_STOPMODE_MASK is the bitmask that was, apparently, intended to simplify access to this 2-bit bitfield. The bits 6,7 can't be considered independently, values XUARTPS_MR_STOPMODE_2_BIT are...