David Kruckemyer

Thanks for your feedback. I have some short responses and some longer responses, and unfortunately, at this time, I can only address the feedback that requires short responses. But I...

Though it can be inferred, I don't believe the spec explicitly states that the "access size" of a CBO is the size of the block. Do folks feel that a...

Addressed in https://github.com/riscv/riscv-isa-manual/pull/1431

This is a good point. Because of migration, you do want an atomic way of determining how much data was operated on. Reading a CSR and executing a CMO is...

I agree, and the key idea is that CMOs ultimately respect the cacheability PMA, even if the PBMTs "downgrade" cacheability to non-cacheable.

I propose devising an abstract cache model on which the CMOs operate. Without such, it's harder to come up with a consistent set of definitions. The abstract model can be...

@AndyGlew re: abstract models.... Not offended. Still going to push for one... :) re: points of coherence.... There are "points of serialization" where request streams from different harts merge. I...

Note that ARM pretty much solves this issue and provides recipes for both the TLB and cache management. The key is that CMOs ignore the cacheability attributes and *always* check...

Addressed in https://github.com/riscv/riscv-isa-manual/pull/1428

What happens on a "PMA _checker_ violation" is well-defined in the priv spec (i.e. access fault), but what happens on an access to a memory location that does not result...