David Kruckemyer

A quick one to address the specification: For management CBOs, the spec does state what happens with the accessed bit and, by omission, what happens with the dirty bit (don't...

One perspective is that management CBOs are not explicit stores, and that the dirty bit is only set when an explicit store is executed. Flush and clean do not change...

> Because an invalidate is a programmer-initiated instruction to potentially change memory, which is a dirtying action in my book Ah, but the semantic intent of invalidate is to discard...

> Now, yes, that's a bit of a contrived sequence, but the point is to demonstrate the nature of the problem. I think the irony is that, by relaxing the...

Still not following. Here's what I think is happening: > 1. Userspace writes value 1 to page The value 1 is either in a cache or in memory. Regardless, that's...

> > > ``` > > > 5. Userspace reads 2 from page (kernel swaps page in but leaves page on disk) > > > ``` > > > >...

> > In the former case, the hart is a consumer (i.e. reader) of data produced by the non-coherent agent > > The sequence for this is: > > 1....

FWIW, this profile option, Zic64b, also indicates the cache block size: https://github.com/riscv/riscv-profiles/issues/37

The intent was the latter (number 2). Since the prefetch instructions are encoded as hints, we don't do any permissions checks, even though the standard address translation applies. The different...

It seems the real performance gains to flushing an entire cache (or possibly even a range?) would be obtained from making the operation asynchronous to the rest of instruction execution....