Dongjoon(DJ) Park
Dongjoon(DJ) Park
This question was posted in https://github.com/Xilinx/Vitis_Embedded_Platform_Source/issues/33, but no one seems to respond the open issues there. So I am reposting the issue here. I built zcu102 dfx platform (22.1 version)...
# Summary I am trying fpga_recompile example and recently upgraded to Quartus Prime Pro 23.1. I used Quartus 22.2 previously and it successfully generated .a file with the command below....
``` 2 1 011 1 2 1 2 1 1 ``` Graph file looks like above. There are only two nodes, one with weight of 1 and another with weight...