David Williams

Thanks for your attention, Jonathan. Also, I want to recognize how much work somebody has done to make all the doc that is there. The site looks beautiful and there's...

A confession: this gateware does not do well when held up for more than a handful of clocks. All the projects I've used it with are dataflow oriented and consume...

Hi! Thanks for taking a look at the code. First... I assume you are using NextPNR. Older code, like Arachne, won't work. Arachne doesn't optimize for clock time! NextPNR does....

Hi Matthais, The code is pretty bratty about being held up. There is no provision to apply back pressure to the USB internals, so the code just gets unhappy when...

Got it. When the FPGA logic is slower than the connection that would be a requirement.

Also it looks like: ``` #define TFT_INVERT_ROTATION1 0 #define TFT_RGB_BGR 0x08 ``` Are better settings for the ILI9341

Could the internal port feature help? https://davidthings.github.io/hdelk/tutorial#internal-ports

Excellent solution. It will be a bodge of honor.

Another wrinkle... leaving open the possibility of user error, Diamond does not have C12 as a Clock pin (B12 is, D12 is, just not C12), and persists in declining to...

No love for two years? Thank you zhuyie. This is a nice addition.