Davide Giri
Hi, thank you for your contacting us. Adding support for more FPGA boards is definitely interesting to us. It can be a difficult job, it really depends on how similar...
Hi! We have not yet explored the integration of NVDLA large (or full) in ESP, although it would be very nice to have. I agree that adding the SRAM should...
Great, that's what I thought. The problem is that I don't think NVDLA large will fit on the VC707. Let us know how it goes and if you have any...
Yes, that is exactly what I was referring to when I mentioned there is some work needed on the main memory interface, where the AXI data bitwidth will increase significantly....
This is a good lead, thank you. Let me see if I find where the ISA gets passed when building BBL/Linux. One place where the ISA definitely gets specified is...
We now allow at most 8 rows and 8 columns in the GUI, so the bug has been fixed (see commit c71f5db) I'm changing the label from bug to enhancement....
Hi, thanks for submitting the pull request! I ran the RTL simulation of the `base_test()` in the pull request with 4 Leon3 cores, but either the simulation got stuck or...
I tested on a Xilinx VC707 with 4 CPU tiles, but it still gets stuck with or without the new prints you added. This is the behavior I observe. What's...
It always hangs and according to the terminal output it's possible it's always getting stuck in the same place.
I'm actually using the RTL cache, I can try with the SystemC cache and see if there are any differences.