David Biancolin

Inlines all of MIDAS scripts. I don't intend to merge this PR, this just makes these scripts accessible to other people. To merge this stuff, i think we should peel...

Add Feature To Optionally Limit ID Reuse in Timing Model

6

Resolves #643, by adding a UserYanker internally to the timing model. This can be optionally disabled in timing models where it safe to have transactions under the same ID in...

Reference targets that are target-side bridge-module local aren't properly renamed onto ports in some cases (e.g, a RT rooted at the RationalClockBridge, pointing at one of it's clocks). Reproduce using...

Mergify Automation for Pulling Forked PRs into Local Ones

4

This will make it easier to run CI on forked PRs without manual intervention.

Add rv64ui-p-simple in FPGA-level simulation to CI

2

FPGA-level simulation is brittle and run rarely. When we do need it, we _really_ need it so it's probably worth forcibly checking that it works in the CI for a...

### Background Work - [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim) - [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues) - [X] Yes, I searched the [documentation](https://docs.fires.im/en/stable/) ### FireSim Version and Hash...

Building these takes 40m right now. Conservatively could rebuild only on Chipyard bumps and be fine.

We want to be able to automatically catch the following: - The driver returning non-zero (any obvious simulation failure) (see 1.13 release) - Erroneous behavior in the target potentially not...

Users may see scala compilation issues that look like: ``` [error] /target-design/chipyard/tools/treadle/src/main/scala/treadle/Driver.scala:6:8: object ExecutionOptionsManager is not a member of package firrtl [error] import firrtl.{AnnotationSeq, ExecutionOptionsManager, HasFirrtlOptions} [error] ^ ``` Explanation...

I'm keeping a list here for future clean up. * midasexamples PointerChaser * Legacy FAME1 transform; use gated clock conversion instead.