David Biancolin comments

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                                            David Biancolin

Assertion-Synthesis.rst needs an update

Those are all good suggestions.

Add Feature To Optionally Limit ID Reuse in Timing Model

@mergifyio rebase

Add Feature To Optionally Limit ID Reuse in Timing Model

@mergifyio rebase

Add Feature To Optionally Limit ID Reuse in Timing Model

@mergifyio rebase

generalize delivering shared libraries to remote nodes

Tied up in discussion about how to deliver drivers to hosts (of different type). Pushing

Add rv64ui-p-simple in FPGA-level simulation to CI

We need access to EC2 instances or vivado licenses to make this possible. Pushing.

Add rv64ui-p-simple in FPGA-level simulation to CI

Think about alongside other host support.

Partially routed net in MemModel

This all started happening because i told Jan Gray that we _weren't_ having problems with multi-SLR designs.

Partially routed net in MemModel

Have you tried the SLR assignment constraint yourself? From Albert's comment it seems like it might not have been applied correctly. How frequently do you see this issue?

Partially routed net in MemModel

I don't really have any leads on this, aside from using placement constraints per the UG. I know upgrading to a newer FireSim version is a large undertaking, but it...