datnguyen263
datnguyen263
have the problem solved?
@doonny i try to make with board DE1_SoC_Opencl v18.1 but error: aoc: Linking with IP library ... Compiler Error: Couldn't achieve user-specified II for loop at c:\Users\PipeCNN\project_intel/c:/Users/PipeCNN/project_intel/device/conv_pipe.cl:751 Error: Verilog generator...
> v18.1 is not supported, please v20.1 @doonny https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=4 I dont have v20.1. How about v16.0 or v14.0?
Do you solved the problem?
> It seems you are building for ARM processor, make sure you have correct cross-compiling env set up . How to check cross-compliling env setup? Tks for your answer!