Daniel Lehmann

armv6m: msr instruction is reading from the wrong register

2

**Describe the bug** `msr apsr, r5` produces the correct disassembly but produces incorrect pcode. See attached screenshots; notice how Input Objects does not list r5, but instead r0. I dug...

PRIMASK is handled incorrectly in Sleigh. From the armv6m manual: * Executing the instruction CPSID i sets PRIMASK.PM to 1. * Executing the instruction CPSIE i sets PRIMASK.PM to 0....

The msr instruction get the output register from the second 16-bit word, but it must come out of the first 16-bit word. This patch fixes the decoding.

LLDB compatibility: Send complete register definitions in target.xml

3

LLDB requires that the full list of registers is provided. For example, for rv32, this string is currently returned: ```rs fn target_description_xml() -> Option