sv-parser
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dalance
SystemVerilog parser library fully compliant with IEEE 1800-2017
Consider following verilog: ``` function [7:0] my_function (input [9:0] a, b, inout c [0:5]); endfunction ``` the parse_sv gives following result for port b: ``` TfPortItem DataTypeOrImplicit DataType ClassType PsClassIdentifier...
Some preprocessor directives seem to give wrong line numbers. ```verilog `default_nettype none module Mod(); endmodule ``` The `default_nettype` get the correct line number, but everything after have line number offset...
When trying to parse the [`snitch` IP](https://github.com/pulp-platform/snitch/tree/master/hw/ip/snitch) I get a parse error, I guess due to the multiple `import` statements? ``` Error: parse error --> /tmp/snitch/hw/ip/snitch/src/snitch.sv:13:60 | 13 | module...
This syntax is accepted by many tools (including Yosys): ``` module m( input a, output b, ); ``` It'd be convenient to support it in sv-parser
sv-parser aims to be fully compliant with IEEE1800-2017 standard. But if someone wants to use this parser to parse Verilog 2001 file, which is subset of SystemVerilog, there is no...
Compilation of this crate is extremely slow to the point of not being able to use an on-the-fly linter at all, making working with this crate difficult. I've run some...
I need to modify gate level netlists by changing the input and output of individual gates. Currently, I'm doing this using PCRE. This is an inelegant and haphazard solution. I'd...
I noticed sv-parser does an excellent job of parsing most of the code in the sv-tests test bench (https://github.com/SymbiFlow/sv-tests). While working to get ivtest clean I noticed there are a...
