rvemu
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d0iasm
RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
Currently, the online demo doesn't support loading img files, only bin files
In [bus.rs](https://github.com/d0iasm/rvemu/blob/main/src/bus.rs), the inclusive `..=` range is used to match what memory region an address is in, but the `_END` constants seem to represent the address one past the end...
**Assembly code to produce this issue and the output of different RISC-V implementation** ``` fclass.s s0, fa3 ---------------------------------------- Reg_name Spike RVEMU FORVIS SAIL x8/s0/fp 200 4 200 200 fadd.s fa6,...
Hi I tried to run your kernel image using qemu but nothing on the screen. ``` qemu-system-riscv64 -machine virt -bios none -kernel kernel -m 32M -smp 1 -nographic -global virtio-mmio.force-legacy=false...
Hi, All the file under tests/resources/original/rv64-* seems to be riscv64 executable files. Since I'm learning risc-v assembly programing. I wonder how can I get the Assembly or C source code...
makes the fcvt.l.* and fcvt.*.l correctly perform signed conversions fixes https://github.com/d0iasm/rvemu/issues/33#issue-2324074572
fixes https://github.com/d0iasm/rvemu/issues/31#issue-2317849751
see for example in https://github.com/d0iasm/rvemu/blob/f55eb5b376f22a73c0cf2630848c03f8d5c93922/src/cpu.rs#L3022 in the spec they are described as for example >[..] FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a **_signed_** [..] 64-bit...
The riscv spec clearly states that > "When multiple floating-point precisions are supported, then valid values of narrower n-bit types, n