signed dword float to and from conversions `fcvt.l.s`, `fcvt.s.l`, `fcvt.l.d`, `fcvt.d.l` perform unsigned conversions instead

[lenawanel]

see for example in

https://github.com/d0iasm/rvemu/blob/f55eb5b376f22a73c0cf2630848c03f8d5c93922/src/cpu.rs#L3022

in the spec they are described as for example

[..] FCVT.L.D converts a double-precision floating-point number in floating-point register rs1 to a signed [..] 64-bit integer [..] in integer register rd.