rvemu
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d0iasm
RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
interrupt.rs line 67 ``` // Set the program counter to the supervisor trap-handler base address (stvec) // depending on the mode. let vector = match cpu.state.read_bit(STVEC, 0) { 1 =>...
When compiling this, I ran the tests, and it passed. However, when trying to run busybear, I was confronted with this error: ./rvemu-cli --kernel /home/judeu/debian-rv64/bbl.bin --file /home/judeu/debian-rv64/busybear.bin pc: 0x0, trap...
In rvemu, div/divu/divw/divuw instructions set DZ bit when dividing by zero. The spec says "The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction...
I've been developing an OS for RISC-V and use OpenSBI and was linked to this a while back and thought it would be an awesome way to have some friends...
The example in the README doesn't seem to work and I wondered if this was known: ``` $ git clone -q https://github.com/d0iasm/rvemu.git && (cd rvemu;make rvemu-cli && ./target/release/rvemu-cli -k bin/linux/bbl.bin...
Hi.. I get a "thread 'main' panicked' error when I try to run the provided linux binary.. I can run a backtrace if requested. ~/projects/rvemu$ ./target/release/rvemu-cli -k bin/linux/bbl.bin -f bin/linux/busybear.bin...
I'm trying to follow the instructions described in [Bare-metal C Program](https://github.com/d0iasm/rvemu#bare-metal-c-program) in README I got the following errors (OS: Ubuntu 20.10 x86_64) ``` root@292c6ad9bfc1:~/workplace/riscv# riscv64-unknown-elf-gcc -S -nostdlib foo.c root@292c6ad9bfc1:~/workplace/riscv# riscv64-unknown-elf-gcc...
This will allow external code to inspect the entire DRAM as a slice. I'm not sure if there will be an issue if code edits the DRAM externally between CPU...
Hi, I followed the instructions and used the image from this issue. https://github.com/LekKit/RVVM/issues/113 And I'm not able to get networking working. Should I use a different image
