Mitch Bailey
Mitch Bailey
No error with magic `8.3.465` and open_pdks `1.0.470` With magic `8.3.478` and open_pdks `1.0.488` there are many errors like these in the gds read feedback ``` box 600480 580159 600800...
Magic 8.3.478 Possibly related to open_pdk `1.0.471` commit `97d0844` on 2024.03.09 The new warning is ``` feedback add "Could not determine device boundary" pale ``` The relevant code seems to...
Magic 8.3.478 ``` ] property none ] Property name one is not defined ``` Expect the error message to be ``` ] Property name none is not defined ```
The `extract unique notopports` directive is used to virtually connect top ports by name if they are not physically connected. Version 8.3.478 extracts unconnected top ports as connected with `extract...
open_pdks `1.0.489` open_pdks `1.0.471` changed diodes from `D` devices to `X` devices. Along with this change, the `pj` parameter was changed to `perim`. open_pdks `1.0.482` changed the netgen compare function...
Up to netgen `1.5.269`, it's possible to call a verilog module from a spice netlist. Here are the results of the verilog cell compare. ``` Class XL_brownout_dig (0): Merged 155...
netgen `1.5.276` For a given set of source netlists, it appears that mixed device types are allowed, but only the first one is used. For example, one netlist may have...
netgen `1.5.276` I intended to add `vssd1_ext`, `vssd2_ext`, `vccd1_ext` and `vccd2_ext` ports to the gl verilog for caravel `chip_io.v`. However, after copying `vccd2_pad` in the port list, I forgot to...
Updated commits. Copied Makefile from digital Added cocotb (including unused digital tests that can serve as a base for new digital circuits). Standardized lvs_config.json, openlane/Makefile, and .gitignore
Updated commits. Standardized lvs_config.json, openlane/Makefile, and .gitignore Removed separate pdk for openlane/LVS functionality. Would result in race conditions for parallel execution.