Mitch Bailey
Mitch Bailey
Here's an example ``` Processing timestamp mismatches: user_id_textblockWarning: Parent cell lists instance of "chip_io" at bad file path /home/user/mpw-9/caravel_user_project3/mag/chip_io.mag. The cell exists in the search paths at ../mag/chip_io.mag. The discovered...
`Magic 8.3 revision 373` The attached gds, when flattened, should extract to a netlist equivalent to (4 nodes, 7 devices) ``` .subckt sky130_fd_io__res250only_small PAD ROUT R3 ROUT_ ROUT sky130_fd_pr__res_generic_m1 w=2.01...
In magic 8.3.328 ``` .subckt sky130_fd_sc_hd__conb_1 LO HI VGND VPWR R0 HI VPWR sky130_fd_pr__res_generic_po w=480000u l=45000u R1 VGND LO sky130_fd_pr__res_generic_po w=480000u l=45000u .ends ``` In magic 8.3.368 (2 `w` parameters)...
The current `openlane/user_project_wrapper/config.json` file has `"SYNTH_ELABORATE_ONLY": 1`. This causes the top level to only be routed and there is no way to add hi/low ties or solve (or maybe even...
Fixes #334
input is disabled. `GPIO_MODE_MGMT_STD_BIDIRECTIONAL` should be `0x005` or `0x00d` `GPIO_MODE_USER_STD_BIDIRECTIONAL` should be `0x004` or `0x00c` (with `OE_OVERRIDE` low, `OUTPUT_enable` is irrelevant.)
branch `gf180mcu` The following `Makefile` line ``` cocotb-dv_patterns=$(shell cd verilog/dv/cocotb && find . -name "*.c" | sed -e 's|^.*/||' -e 's/.c//') ``` always throws this error because the `verilog/dv/cocotb` does...
Fixes #324
The default `OPEN_PDK_COMMIT` in the `Makefile` references a pdk `78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc` that is missing `libs.ref/sky130_sram_macros/maglef` directory. ``` $ volare ls In /volare/sky130/versions: └── 78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc (2023.07.10) (enabled) $ ls $PDK_ROOT/$PDK/libs.ref/sky130_sram_macros/ gds lef...
NOTE: Probably not the correct repo to flag this issue. I believe [https://foss-eda-tools.googlesource.com/third_party/shuttle](https://foss-eda-tools.googlesource.com/third_party/shuttle) is intended to be a snapshot of the repo for each of the designs on a shuttle...