cxzzzz

UserInterruptPlugin Interrupt Enable Problem

1

hi, i notice that when adding a user-defined interrupt using UserInterruptPlugin, it just use the `interruptPending` as the cond signal ,without any enable signal as a gate controller https://github.com/SpinalHDL/VexRiscv/blob/98de02051e1a5c9400c022dc61acd4bd0507f8a5/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L1153-L1155 it...