William D. Jones
William D. Jones
Actually, I believe the [this patch](https://github.com/pypa/setuptools_scm/pull/520#issue-803869301) will also fix the issue here (use `--show-prefix` instead of `--show-toplevel` and reconstruct an absolute path from within Python). EDIT: Workaround for now: `PDM_BUILD_SCM_VERSION=2.1.7.dev...
Alternate (better) workaround: Install an alternate git, like the [Portable](https://git-scm.com/download/win) Windows download, decompress, and then prepend the binary directory to your `PATH` so that PDM finds and uses the alternate...
> This still needs to be documented, so I'll keep it open for now. Will generator functions be deprecated in 0.6 instead of 0.5? `async` testbenches made the 0.5 cutoff,...
I also ran into issues with the `xcffib` dep today while building documentation for a LiteX SoC: ```cmd Generate the documentation by running `sphinx-build -M html C:/msys64/home/William/Projects/FPGA/litex/SoCs/orangecrab-feather/build/gsd_orangecrab/doc/ C:/msys64/home/William/Projects/FPGA/litex/SoCs/orangecrab-feather/build/gsd_orangecrab/doc/_build` identifier_mem@f0003000: Found...
FWIW, I was able to get `sphinx-wavedrom` to install, and the example to compile on Windows 10 with the following patch: ```diff diff --git a/example/source/conf.py b/example/source/conf.py index bb235e9..4566cf1 100644 ---...
A workaround to using Record.raw_bits() is to iterate over a record's subsignals using Record.iter_flat(). Using the above gist as an example, replace the line `self.specials += [self.iobufs[i].get_tristate(self.pins[i])]` with the following...
@jordens You may be right. FWIW, I have found another edge case where the same invalid Verilog idiom will be generated when dealing with tristates: https://gist.github.com/cr1901/3a666c635f956fa6a819
>hmm, having a 4KB 2-way instruction cache could be realy usefull if the ROM is on a external SPI chip, then keeping the remaining of the ram-blocks as a data...
@mithro With PR #3 being merged, this is effectively done. Of course, still need to test them all :). Also note that the `Min` core does not have a multiplier/divider...
@Dolu1990 ~We still need the actual module name inside the output Verilog file to be `Vexriscv`, even if the output filename changes for each configuration. Could you add a `moduleName`...