Kefa Chen

Hello, @hossein1387, I try to merge your PR with ara locally, but get error when synthesis. Vivado complains it can't find module `tc_clk_gating` ```shell ERROR: [Synth 8-439] module 'tc_clk_gating' not...

> > Hello, @hossein1387, I try to merge your PR with ara locally, but get error when synthesis. Vivado complains it can't find module `tc_clk_gating` > > ```shell > >...

Hello @hossein1387 , I recently try to synthesis this design on my genesys2 board. When I tried add a new `xdc` file, I had some questions about `xcvu9p.svh` and `xcu280.svh`...

Hi, recently I have generated bitstream on board genesys2 successfully. If my understanding is correct, current soc only has a uart and xilinx sram in place of ddr memory, and...

Hi, it seems that verilator only support unpacked struct or union by this [commit](https://github.com/verilator/verilator/commit/c2b09e35f8c3fb1be724ebd3b74465773d5c1894). If no one is working on this, I'd like to make a patch for support on...

Thank you for the informative reply! It reminds me of endianness and `VlWide` class. I would revise expected goal of exporting packed struct / union as **making sure that a...

> What is not specified by C/C++ is the ordering of bitfields in C structs. Yes, but I think (by some tests) the implementation is the same for gcc and...

Because C++ don't specify the storage layout of bitfield. If we want to fill the bitfield of struct and use a simple `memcpy` to transfer data into `VlWide` class, there...

Or, instead of exporting pure struct and relying on unportable bitfield storage layout, we could export a class with the same storage layout as internal representation of verilator and some...

Hi @Sustrak. Thank you for your points and I didn't know this tool before. I have tried the `slang-reflect` and it's indeed helpful in some degree. And it will be...