Ckristian Duran

Enable a way to configure the Cache characteristics from the Ibex Core Top

4

Simply I noticed this in the Ibex. The cache is fixed always to: ``` module ibex_icache #( // Cache arrangement parameters parameter int unsigned BusWidth = 32, parameter int unsigned...

Fixes to support TSMC18 technology port

1

List of changes: hierarchy_layout.py: - Support for the minimal areas. Only activated to "tsmc18" strings in the tech_name. pgate.py: - Whenever a port is created in any gate, it does...

sg13g2_io sg13g2_IOPadAnalog has minor DRC errors

5

Cell `sg13g2_IOPadAnalog` has minor DRC errors from the dev branch: `Sdiod.d` and `Sdiod.e`. Probably is not noticeable in a normal digital run because there are no digital circuits using this...