Kenta IDA

Hi, I found that the root cause of this issue is just initialization code of `TFT_eSPI::gfxFont` is missing in its constructor. Adding `gfxFont = NULL;` before the line 269 of...

Chiselの生成したVerilog HDLは読めないけど、Verylのは読めるみたいな話があるといいんですかね。 実際のところ、言い方はアレですが、VerylからSystemVerilogに’戻りたくなっても何とかなるだろうと思って触り始めてるというのはあります。最悪、どこかの時点でVerylが生成したSVコードをもとにSystemVerilogのみの開発に戻ればいいだろうと。 この辺も "漸進的" という利点に含まれるのかなと思います。

Thanks for providing the pre-build bitstream. I've modified the physical constraint and comment out `define dvk_brd` line in `top_define.v` this morning and the board got recognized as a PCIe device....

The number shown by this line of `loop.sh`. I think it means number of runs of DMA transfer test. https://github.com/sipeed/TangMega-138KPro-example/blob/main/pcie/PCIe2.0_dma_demo/gowin_pcie_demo/gowin_pcie_demo/loop.sh#L11 I confirmed that my board was recognized as a PCIe...

So, is it by design? As @Dominaezzz pointed out, many affordable embedded devices with SPI LCD face the same issue. (I believe there are numerous ESP32 boards with a similar...

@bugadani I'm not sure why the `D/CX` signal in the timing diagram doesn't specify the level while reading parameters. However, according to the command list and the description of `Read...