chmousset

@enjoy-digital sure, I can send you the HW. I've sent you an email to arrange shipping.

@xobs Thanks for the review >There was a program that was presented at Latchup 2023 that I am having trouble finding now. It was a browser-based register explorer. https://github.com/SystemRDL/PeakRDL-html ?...

same thing here with fr layout. Older (March 2023) release of Lapce worked correctly. ``` > setxkbmap -query  ✔ rules: evdev model: pc104 layout: fr ```

@andelf has there been any significant advancement on the Ethernet part? I've been looking a bit into Ethernet for the CH32V208 on my side. As [others pointed out](https://www.eevblog.com/forum/microcontrollers/ch32v307-risc-v-minicore-with-ethernet/msg5181855/#msg5181855), it seems...

@christopherkutzmann not much. I did a little digging and here are my notes: CH32 have two Ethernet controllers: - A 10M MAC + PHY, no MII interface - present in...

TX works on the CH32V208! Well, sort of: there is still a lot of work to be done before there is a clean HAL though. experimentation project: https://github.com/chmousset/rs-ch32v208-eth MAC-10M register...

would love to have this aswell; it's currently blocking me from adding Ethernet support

Nice to see CAN is coming to ch32-hal! I'm testing the paval-shlyk:ch32-hal:main branch, with both CAN interfaces connected to the same bus. Each CAN peripheral can emit frames, and ACK...

@mickeprag I tested with a single CAN at a time. In that case, it looks like it's related to FIFO1: | CAN | FIFO | RX ACK | RX Data...

@mickeprag did you have the occasion to look into it? Anything I can do to help?