Array assignment to wires - parse error on `=`

[hzeller]

Seen in the wild: code like this:

module foo();
 wire [8:0] someval[2] = '{42, 43}; 
endmodule

... which results in a syntax error:

/tmp/foo.sv:2:24: syntax error at token "="

Not sure how valid of system verilog code that is, or if this is just something some vendors support, but if it is something that is supported by some, maybe we should also support it. Finding LRM spec might also be good.

[hzeller]

@snsokolov you probably know how legal of a construct it is. I seems to be accepted by at least some proprietary tools, so I guess it is. I typically just never came across it. I suspect it mostly something that also can/should be localparams ?