How can I parse only verilog and not systemverilog?

[arunpatro]

Hi,

I want to restrict my application to only verilog programs and not system verilog, can you help me figure out the grammar specification for only .v files?

[hzeller]

Currently, we don't distinguish different dialects, so that can mean that valid Verilog programs might not be parsed correctly with Verible.

Is there a particular construct that you found Verible does not like in your Verilog files ?

It is on our TODOs since #141 - but of course that takes time. Happy to accept pull requests.