Port not completely aligned when `input/output var logic xxxx`

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Test case

// Input to the formatter, preferably a reduced test case.
    input var  logic rw1_clock,
    input var  logic                  rw1_enable,
    input var  logic rw1_write,
    input var  logic [ADDR_WIDTH-1:0] rw1_addr,
    input var  logic [MASK_WIDTH-1:0] rw1_mask,
    input var  logic [DATA_WIDTH-1:0] rw1_dataIn,
    output var logic [DATA_WIDTH-1:0] rw1_dataOut,

Format the above code.

Actual output

// This doesn't look right.
    input var  logic                  rw1_clock,
    input var  logic                  rw1_enable,
    input var  logic                  rw1_write,
    input var  logic [ADDR_WIDTH-1:0] rw1_addr,
    input var  logic [MASK_WIDTH-1:0] rw1_mask,
    input var  logic [DATA_WIDTH-1:0] rw1_dataIn,
    output var logic [DATA_WIDTH-1:0] rw1_dataOut,

The column of var is unaligned.

Expected or suggested output

// This result would look better from the formatter.
    input  var logic                  rw1_clock,
    input  var logic                  rw1_enable,
    input  var logic                  rw1_write,
    input  var logic [ADDR_WIDTH-1:0] rw1_addr,
    input  var logic [MASK_WIDTH-1:0] rw1_mask,
    input  var logic [DATA_WIDTH-1:0] rw1_dataIn,
    output var logic [DATA_WIDTH-1:0] rw1_dataOut,

vars are also should be aligned.