Parser cannot handle `ifdef conditions inside concatenation assignments

[AlistairSymonds]

Describe the bug

Parser cannot handle `ifdef conditions inside concatenation assignments. Originally encountered this when looking at formatting a larger file, but the same issue can be seen in this example just using the parser.

To Reproduce my_mod.sv:

module my_mod();
   logic [1:0] a = {
      `ifdef MY_DEFINE
      1'b0,
      `endif
      1'b1
   };
endmodule

Actual behavior:

alsy@Neon:~$ verible-v0.0-2039-g77748efe/bin/verible-verilog-syntax my_mod.sv
my_mod.sv:3:7-12: syntax error at token "`ifdef"

Expected behavior

Not error out - looking at the printed tree with the ifdef moved to encapsulate the entire body so it parses - it looks like it would make sense to have the entire first kExpression in the kConcatExpr exist under a kPreProcessorIfdefClause. Not sure how much messier that would make using parsed output since there could be PP clauses everywhere, but I'm not sure of a better option and I imagine every other bit of parsed code could also have this issue.