Design of Profiler

[FanShupei]

Tracking issue for OSPP 2024 Profiler for T1.

Prof Event Collecting

After discussion with Sequencer, the profiler will NOT use json-based events (unlike offline verifier). Since profiling events is much more than verification events, the json format is slow and bloated. The json-based event is currently exclusively for verification.

Instead, profiler will read from wavedump directly. Note T1 is written in Chisel. After Chisel -> SV lowering, the hierarchy and signal of generated VS is not guaranteed. . In this design, we could give guarantee to the naming of signals using Chisel tricks, and we could dump only profile-related signals to speed up simulation.

Perf Event

We plan to collect perf data from various components.

• Issue/Retire Queue: analyze interaction with the scalar core
• VLSU: analyze stall due to memory access
• VRF: analyze stall due to VRF access conflict
• VEXU and soreboards: analyze VEXU utilization rate and chaining statistics

Analyse Results

Per-cycle statistics: Essentially just "beautified" version of raw profiling signals. It will be generated in waveform format, intended to view with RTL wavedump simultaneously.

Overall statistics: use simplified version of top-down microarchitecture analysis.

Roadmap

• Prof Event Collecting
  • [ ] perfdata module refactor (collaborate with RTL folks)
  • [ ] wavefile reader
• Prof Result Output
  • [x] FST wavefile writer
  • [ ] other format (e.g. VCD) writer
• Dramsim Integration
  • [ ] dramsim integration in dpi driver
• Topdown Analysis
  • [ ] implement top-down analysis