SystemVerilog accessing slice of Union member not handled

[rherveille]

I got an error "Accessing member of a slice of type AST_UNION is unsupported. This is triggered in uhdm_ast.cc I believe changing line 965 else if (current_struct_elem->type == AST::AST_STRUCT) to else if (current_struct_elem->type == AST::AST_STRUCT || current_struct_elem->type == AST::AST_UNION) fixes this. At least in my use case.