Formal equiv diff hier_path

[alaindargelas]

Testcase: ./yosys/tests/simple/module_scope.v Trimmed down to the following example:

module module_scope_Example(o1);
   parameter [31:0] v1 = 10;
   output wire [31:0] o1;
   assign module_scope_Example.o1 = module_scope_Example.v1;
endmodule

module module_scope_top(
   output wire [31:0] a1
);
   module_scope_Example a(a1);
endmodule

The latest Surelog does not duplicate the assign statement (That was a bug), now the plugin does not find the parameter constant and assigns 32'hxxxx to o1 instead of 32'd10.

The UHDM tree is correct with the exception that there is no binding for the module reference which I think is not necessary for the plugin:

...
    \_cont_assign: , id:79, line:4:11, endln:4:60
      |vpiParent:
      \_module: work@module_scope_Example (work@module_scope_top.a), id:68, file:tests/ScratchPad.sv, line:10:4, endln:10:31
      |vpiRhs:
      \_hier_path: (module_scope_Example.v1), id:83, line:4:37, endln:4:60
        |vpiParent:
        \_cont_assign: , id:79, line:4:11, endln:4:60
        |vpiName:module_scope_Example.v1
        |vpiActual:
        \_ref_obj: (module_scope_Example), id:84, line:4:37, endln:4:57
          |vpiParent:
          \_hier_path: (module_scope_Example.v1), id:83, line:4:37, endln:4:60    <<< Missing actual 
          |vpiName:module_scope_Example
        |vpiActual:
        \_ref_obj: (v1), id:85, line:4:58, endln:4:60
          |vpiParent:
          \_hier_path: (module_scope_Example.v1), id:83, line:4:37, endln:4:60
          |vpiName:v1
          |vpiActual:
          \_parameter: (work@module_scope_top.a.v1), id:69, line:2:21, endln:2:23
      |vpiLhs:
      \_hier_path: (module_scope_Example.o1), id:80, line:4:11, endln:4:34
        |vpiParent:
        \_cont_assign: , id:79, line:4:11, endln:4:60
        |vpiName:module_scope_Example.o1
        |vpiActual:
        \_ref_obj: (module_scope_Example), id:81
          |vpiParent:
          \_hier_path: (module_scope_Example.o1), id:80, line:4:11, endln:4:34   <<< Missing actual 
          |vpiName:module_scope_Example
        |vpiActual:
        \_ref_obj: (o1), id:82
          |vpiParent:
          \_hier_path: (module_scope_Example.o1), id:80, line:4:11, endln:4:34
          |vpiName:o1
          |vpiActual:
          \_logic_net: (work@module_scope_top.a.o1), id:47, line:1:29, endln:1:31