synlig
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chipsalliance
SystemVerilog support for Yosys
Hi, I am trying to synthesis a systemverilog design with synlig (https://github.com/dpetrisko/tt07-dll/tree/main). With the plugin installed from main, the design is able to parse and synthesize to completion. Unfortunately, the...
Main change is that Yosys changed how ranges are stored.
I've installed `yosys`. I've installed the `systemverilog` plugin from `https://github.com/chipsalliance/synlig`. I can load the plugin, but then it can't find the `top` module. ``` yosys -p "plugin -i systemverilog" -p...
When I tried to read the SystemVerilog code below, I got a segmentation fault without any error message. Since it contains the non-synthesizable language construct, `bind`, I guess the situation...
I'm on a Mac with the Apple M2 chip. Running the install script does install the plugin, but it's not compatible with the system. Install: ``` curl https://api.github.com/repos/chipsalliance/synlig/releases/latest | jq...
``` $ make -f cmake-makefile cmake -DCMAKE_BUILD_TYPE=Release -DCPU_CORES=12 -DYOSYS_CONFIG= \ -DYOSYS_PATH= -DCMAKE_INSTALL_PREFIX=/usr/local \ -DCMAKE_RULE_MESSAGES=on -S . -B build Using Vendored YOSYS YOSYS_CONFIG: /Users/gus/synlig/third_party/yosys/yosys-config YOSYS_INCLUDE_DIR: /Users/gus/synlig/third_party/yosys Building Synlig version v1.82 []...
### Version Latest release (2024-03-13-d844d8d) with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os) ### Reproduction Steps SystemVerilog code `ccsds_turbo_enc_paddr_gen.sv`: (Origin: https://github.com/dshekhalev/FEC/blob/main/rtl/ccsds_turbo/enc/ccsds_turbo_enc_paddr_gen.sv) ```systemverilog module ccsds_turbo_enc_paddr_gen(iP); parameter int cW =...
### Version Latest release (2024-03-13-d844d8d) with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os) ### Reproduction Steps SystemVerilog code `ucsbece154b_victim_cache.sv`: (Origin: https://github.com/sifferman/labs-with-cva6/blob/main/labs/caching/part2/starter/ucsbece154b_victim_cache.sv) ```systemverilog module ucsbece154b_victim_cache( input logic [7:0] raddr_i...
### Version Latest release (2024-03-13-d844d8d) with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os) ### Reproduction Steps SystemVerilog code `top.sv`: ```systemverilog module top(output int o); typedef struct packed {...
This looks relevant to #768 and #689, yet is caused by different language constructs. ### Version Latest release (2024-03-13-d844d8d) with Yosys 0.36+58 (git sha1 ea7818d31, clang 14.0.6 -fPIC -Os) ###...