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Fix python wide-number assert on 11.4.14.3--unpack_stream_pad-sim.sv
Fix 11.4.14.3--unpack_stream_pad-sim. Although there is some support for wide numbers, the assert here was miscalculated in the test driver, so moving the check into Verilog.
Changes In Tests
| Tool | New Failures | New Passes | Added | Removed | Not Affected |
|---|---|---|---|---|---|
| sv_parser | 0 | 0 | 0 | 0 | 5011 |
| Slang | 0 | 0 | 0 | 0 | 5074 |
| Odin | 0 | 0 | 0 | 0 | 5011 |
| Surelog | 0 | 0 | 0 | 0 | 5074 |
| moore | 0 | 0 | 0 | 0 | 5011 |
| circt_verilog | 0 | 0 | 0 | 0 | 5073 |
| tree_sitter_systemverilog | 3 | 13 | 0 | 0 | 4901 |
| SynligYosys | 0 | 1 | 0 | 0 | 4731 |
| Sv2v_zachjs | 0 | 0 | 0 | 0 | 5074 |
| Icarus | 0 | 0 | 0 | 0 | 5079 |
| yosys_slang | 0 | 0 | 0 | 0 | 4270 |
| tree_sitter_verilog | 0 | 0 | 0 | 0 | 4920 |
| Slang_parse | 0 | 0 | 0 | 0 | 5011 |
| Verible | 0 | 0 | 0 | 0 | 4920 |
| Yosys | 1 | 0 | 0 | 0 | 4732 |
| moore_parse | 0 | 0 | 0 | 0 | 4920 |
| VeribleExtractor | 0 | 0 | 0 | 0 | 4920 |
| Verilator | 0 | 1 | 0 | 0 | 5078 |
@kbieganski should be good to merge, thanks.