chipsalliance
Prioritize coprocessor FPU reqs over core FPU reqs
This avoids deadlock conditions due to coprocessor requests typically being from older instructions.
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Type of change: bug report | feature request | other enhancement
Impact: no functional change | API addition (no impact on existing code) | API modification
Development Phase: proposal | implementation
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But why it will deadlock, I don't understand. It sounds like the deadlock is coming from the structural hazard between scalar and vec/rocc. However they basically has no real dependencies?
Suppose a older vector is trying to use the FPU, while the core is trying to execute a younger vector instruction, which needs the FPU at the X stage to access the FP operand. If the younger instruction is given priority, it will read the operand, but then potentially stall+replay at the W stage due to vector unit being busy.
Generally, in such a simple pipeline, prioritizing the oldest in-flight operation will avoid deadock conditions.