firrtl

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### Checklist - [ ] Did you specify the current behavior? - [ ] Did you specify the expected behavior? - [ ] Did you provide a code example showing...

ekiwi

Add option to ignore undeserializable annotations (basically pass them through)

2

### Checklist - [ ] Did you write out a description of the feature you want to see? - [ ] Did you look around for any related features? -...

jackkoenig

This is an automatic backport of pull request #2381 done by [Mergify](https://mergify.io). --- Mergify commands and options More conditions and actions can be found in the [documentation](https://docs.mergify.io/). You can also...

mergify[bot]

This is an automatic backport of pull request #2381 done by [Mergify](https://mergify.io). Cherry-pick of ef1d27a84addc46353884eb06ea18f4c68e6a808 has failed: ``` On branch mergify/bp/1.3.x/pr-2381 Your branch is up to date with 'origin/1.3.x'. You...

mergify[bot]

If you compile the following circuit with `-X mverilog` (which will disable DCE), you get a match error inside the Verilog emitter: ```scala circuit Foo : module Bar : input...

seldridge

Jack and I talked about this on Gitter. We think that randomization should be opt-out instead of opt-in.

ekiwi

Usage instructions for ReplSeqMemsAnnotation are incorrect

1

### Checklist - [x] Did you specify the current behavior? - [x] Did you specify the expected behavior? - [ ] Did you provide a code example showing the problem?...

mwachs5

Seems like `InlineInstances` adds wires to the circuit, but does not declare that it invalidates the `RemoveWires` pass. The easy fix would be to add the invalidation. However, it would...

ekiwi

### Checklist - [ ] Did you specify the current behavior? - [ ] Did you specify the expected behavior? - [ ] Did you provide a code example showing...

mwachs5

Division width in generated verilog

2

### Checklist - [x] Did you specify the current behavior? - [x] Did you specify the expected behavior? - [x] Did you provide a code example showing the problem? -...

davidmetz