Fixed Printing

[seldridge]

Trying to printf a Fixed type fails CheckTypes. There isn't a fundamental reason for why FIRRTL can't print Fixed types, but this would require some special handling for

Type of issue: bug report | feature request

If the current behavior is a bug, please provide the steps to reproduce the problem:

Try to printf a Fixed type.

• If possible, please directly provide the FIRRTL file or a relevant fragment if the file is large

The following is the output from a small Chisel module that printfs some fixed point data types.

circuit FUSubFVerbose : 
  module FUSubFVerbose : 
    input clock : Clock
    input reset : UInt<1>
    output io : {flip a : Fixed<16><<7>>, flip b : Fixed<16><<7>>, out : Fixed<16><<7>>}
    
    node _T = sub(io.a, io.b)
    node _T_1 = tail(_T, 1)
    node _T_2 = asFixedPoint(_T_1, 7)
    io.out <= _T_2
    node _T_3 = bits(reset, 0, 0)
    node _T_4 = eq(_T_3, UInt<1>("h00"))
    when _T_4 :
      printf(clock, UInt<1>(1), "%x + %x = %x\n", io.a, io.b, io.out)
      skip

• What is the current behavior?

CheckTypes fails as only ground types (UInt/SInt) can be printed.

[error] (run-main-3) firrtl.passes.CheckTypes$PrintfArgNotGround: : [module FUSubFVerbose]  Printf arguments must be either UIntType or SIntType.

• What is the expected behavior?

You should be able to print out fixed point datatypes. This would likely require a relaxation of CheckTypes on HighForm as fixed point won't be converted to SInts until later. How to interpret a %x or %d format and convert it properly for a fixed point type is open to discussion.

What is the use case for changing the behavior?

It would be nice to be able to print Fixed types without having to manually extract bits.

Impact: API addition (no impact on existing code)

Development Phase: request

Other Info:

This could be viewed as a code generation problem for Chisel and not a FIRRTL issue. I.e., Chisel should be handling printfs that involve FixedPoint types differently.

[mvanbeirendonck]

I'm putting a note link here to https://github.com/chipsalliance/chisel/issues/3161. It looks advantageous to tackle these two issues together.