firrtl-spec
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chipsalliance
The specification for the FIRRTL language
Add missing CHIRRTL memories to the spec. Consider reworking these to use the CIRCT interpretation of them that makes handling simpler.
This PR removes `message` field in cover, according to [reply](https://github.com/chipsalliance/chisel3/pull/2912#issuecomment-1366303618) from @ekiwi: > How is this message supposed to be displayed by different backends like SymbiYosys or Jasper Gold? The...
A circuit that includes a Verilog-illegal defname in an extmodule should be handled or rejected. This depends on the interpretation of whether the `defname` is the "Verilog name" or if...
It seems like the ABI would be the right place for placing rules on how names for wires, registers, modules, etc are lowered to SystemVerilog. There was a suggestion as...
There are a bunch of defines that FIRRTL compilers emit for controlling different randomization/initial behavior. Enshrine these in the ABI document.
This PR changes memory statements in FIRRTL to allow more fine-grind control over parameters on memories, allowing: - Per-port read / write latency - Write ports with no masks In...
Add a YAML formatter like https://github.com/google/yamlfmt that runs on all the yaml configuration files in the repo. Add a check that this causes CI to fail if the YAML is...
There has been great discussion about this topic on #75 , but it is a separate idea so I thought we'd move the conversation to a dedicated issue. ## Background...
Add a string type to the FIRRTL spec. This is intended to clarify the type of an external module's string parameter as well as the type of the argument to...