f4pga-sdf-timing
f4pga-sdf-timing copied to clipboard
Create a SDF file canonicalizer
We need a tool which takes a SDF file and generates a "canonical" form. It probably wants to sort via INSTANCE
and then CELLTYPE
.
Currently we get SLICEL and SLICEM timing information stored together;
(CELL
(CELLTYPE "SELMUX2_1")
(INSTANCE SLICEL/F7AMUX)
(DELAY
(ABSOLUTE
(IOPATH 0 OUT (0.053::0.067)(0.153::0.190))
(IOPATH 1 OUT (0.055::0.069)(0.156::0.193))
(IOPATH S0 OUT (0.085::0.106)(0.222::0.276))
)
)
)
(CELL
(CELLTYPE "LUT_OR_MEM5LRAM")
(INSTANCE SLICEM/B5LUT)
(DELAY
(ABSOLUTE
(IOPATH A1 O5 (0.045::0.056)(0.122::0.152))
(IOPATH A2 O5 (0.044::0.055)(0.122::0.152))
(IOPATH A3 O5 (0.043::0.053)(0.121::0.150))
(IOPATH A4 O5 (0.047::0.058)(0.121::0.150))
(IOPATH A5 O5 (0.048::0.060)(0.094::0.117))
(IOPATH CLK O5 (0.348::0.434)(0.957::1.187))
)
)
(TIMINGCHECK
(HOLD CLK (posedge CLK) (0.154::0.191))
(SETUP CLK (posedge CLK) (0.250::0.311))
)
)
(CELL
(CELLTYPE "LUT_OR_MEM5SHFREG")
(INSTANCE SLICEM/B5LUT)
(DELAY
(ABSOLUTE
(IOPATH CLK O5 (0.439::0.547)(1.190::1.476))
)
)
(TIMINGCHECK
(HOLD CLK (posedge CLK) (0.070::0.087))
(SETUP CLK (posedge CLK) (0.126::0.156))
)
)
(CELL
(CELLTYPE "LUT6")
(INSTANCE SLICEL/C6LUT)
(DELAY
(ABSOLUTE
(IOPATH A1 O6 (0.045::0.056)(0.100::0.124))
(IOPATH A2 O6 (0.045::0.056)(0.100::0.124))
(IOPATH A3 O6 (0.045::0.056)(0.100::0.124))
(IOPATH A4 O6 (0.045::0.056)(0.100::0.124))
(IOPATH A5 O6 (0.045::0.056)(0.100::0.124))
(IOPATH A6 O6 (0.045::0.056)(0.100::0.124))
)
)
)
a basic version of such tool already exists see: https://github.com/SymbiFlow/prjxray/blob/master/utils/sdfmerge.py
@mithro do you think it should be part of this lib?
GitHub
Documenting the Xilinx 7-series bit-stream format. - SymbiFlow/prjxray
@kgugala Yes.