Path of FixedIO's io generated invalid target

[dtzSiFive]

Type of issue: Bug Report

Please provide the steps to reproduce the problem:

Run this:

//> using repository "sonatype-s01:snapshots"
//> using scala "2.13.14"
//> using dep "org.chipsalliance::chisel:7.0.0-M2+364-7b029eed-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin:7.0.0-M2+364-7b029eed-SNAPSHOT"

import chisel3._
import chisel3.properties.{Path, Property}
import circt.stage.ChiselStage

class TargetIO(width: Int) extends Bundle {
  val in = Flipped(UInt(width.W))
  val out = UInt(width.W)
}

class VerifTarget extends FixedIORawModule[TargetIO](new TargetIO(8)) {
  io.out := io.in

  val p = Wire(Output(Property[Path]()))
  p := Property(Path(io))
}

object Main extends App {
  println(ChiselStage.emitCHIRRTL(new VerifTarget))
}

What is the current behavior?

Produces:

FIRRTL version 4.2.0
circuit VerifTarget :
  ; (removed layer decls)
  public module VerifTarget :
    input in : UInt<8>
    output out : UInt<8>

    connect out, in
    wire p : Path
    propassign p, path("OMReferenceTarget:~_$$View$$_|_$$AbsoluteView$$_>view")

The path("OMReferenceTarget:~_$$View$$_|_$$AbsoluteView$$_>view") is the issue.

What is the expected behavior?

Valid path, or error if unsupported/invalid.

Please tell us about your environment:

Other Information

What is the use case for changing the behavior?