Memories are merge into single one after FIRRTL stage

[ardacekic]

we are using --infer-rw --repl-seq-mem to infer the SRAMs to replace the SyncReadMem in Chisel. However, we have the following issues when using the generated verilog for SRAMs by FIRRTL transform.

When two SRAMs generated with same depth and width but names are different in CHISEL, after FIRRTL pass, we are seeing only one SRAM in verilog, both two implementations are using the same SRAM. How can we see both two SRAMS in the verilog, because two of this same depth, width SRAMs will be generated different technology.So it is important to FIRRTIL not to optimize these.