Chisel5.1.0 cannot emit verilog

[isjcliu]

chisel5.1.0 firtool 1.4.3 In the source code, the emitverilog function is a systemverilog instead of verilog. I changed it to verilog, but the generated .v file is not available in vivado and contains the syntax of systemverilog

[Gary2342]

I have the same problem. Do you find the way to solve this? I find the answer ( #3706 )about this problem saying chisel can only generate systemverilog?

[Emin017]

You can add firtool option to convert unwanted system verilog syntax

[Gary2342]

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[zhongwujie]

To avoid the generation of systemverilog syntax like "automatic logic", you can add

firtoolOpts = Array("-lowering-options=disallowLocalVariables")

[Gary2342]

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