Improve CHIRRTL Emission of Invalidated Aggregates

[seldridge]

Currently, aggregates that are invalidated are emitted as invalidation of leaves. This can result in some very long invalidations when a single invalidation would do.

Consider:

//> using scala "2.13.11"
//> using repository sonatype-s01:snapshots
//> using lib "org.chipsalliance::chisel::6.0.0-M3+55-6dbbc73c-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin::6.0.0-M3+55-6dbbc73c-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import circt.stage.ChiselStage

class Foo extends Module {
  val out = IO(Vec(2, Vec(2, Vec(2, UInt(1.W)))))

  out := DontCare
}

object Main extends App {
  println(ChiselStage.emitCHIRRTL(new Foo))
}

Currently this emits (running the above with scala-cli Foo.scala | sed 's/@.*//'):

FIRRTL version 3.3.0
circuit Foo :
  module Foo :
    input clock : Clock
    input reset : UInt<1>
    output out : UInt<1>[2][2][2] 

    invalidate out[0][0][0] 
    invalidate out[0][0][1] 
    invalidate out[0][1][0] 
    invalidate out[0][1][1] 
    invalidate out[1][0][0] 
    invalidate out[1][0][1] 
    invalidate out[1][1][0] 
    invalidate out[1][1][1] 

This should emit:

FIRRTL version 3.3.0
circuit Foo :
  module Foo :
    input clock : Clock
    input reset : UInt<1>
    output out : UInt<1>[2][2][2] 

    invalidate out