VeeRwolf

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simple_spi.v file not found .vh files not found uart_top not found swerv_wrapper_dmi not found

Sesib

axi/wb bus cycle times

7

I have your design running in nexys A7 with an EL2 core. When I do a sequence of writes to an I/O port, such as GPIO, and my code is...

jamesbbecker

bscan_tap module - how does it work?

21

Hi Olof, I'm new in FPGAs and wondering how does your bscan_tap module work ? where are the definitions / descriptions of the BSCAN2 modules? How are some internal wires...

agrobman

This is not a bug report, I would like some help reading the implementation. I would like to study the data cache and memory controller subsystem. The aim of my...

jeras

fusesoc run --target=basys3 with vivado 2021.2

5

/tools/Xilinx/Vivado/2021.2/bin/rdiArgs.sh: line 311: 8214 Killed "$RDI_PROG" "$@" [Mon Nov 8 11:38:08 2021] synth_1 finished WARNING: [Vivado 12-8222] Failed run(s) : 'synth_1' wait_on_runs: Time (s): cpu = 00:01:22 ; elapsed =...

kendallgreen

[Nexys4 DDR] Struggling to load into ICCM (address 0xEE000000)

3

Hi all, I've been interested in running some tests on the SweRVolf, and have been succesfully programming it within the RAM region (0x00000000-0x07FFFFFF) and the DCCM region (0xF0040000-0xF004FFFF). However, as...

mablinov

With EH1 it works but after changed to EL2, it failed with the following errors. Please let me know your advice. NFO: Programming part xc7a100tcsg324-1 with bitstream swervolf_0.7.3.bit INFO: [Labtools...

nicolast0604

fusesoc run --target=nexys_a7 swervolf with Vivado 2020.1

2

================================================================================ INFO: Wrote dependency graph to /home/nicolast0604/swervolf/build/swervolf_0.7.3/nexys_a7-vivado/swervolf_0.7.3.deps-after-generators.dot INFO: Wrote Makefile fragment to /home/nicolast0604/swervolf/build/swervolf_0.7.3/nexys_a7-vivado/core-deps.mk INFO: Setting up project INFO: Building vivado -notrace -mode batch -source swervolf_0.7.3.tcl /bin/bash: vivado: command not found...

nicolast0604

Do you have any plan to support SweRV-EH2.

2

Hi, Do you have any plan to support SweRV-EH2. Thanks.

nicolast0604

Fusesoc Simulation Error

1

**$ fusesoc run --target=sim swervolf** INFO: Preparing ::cdc_utils:0.1 INFO: Downloading fusesoc/cdc_utils from github INFO: Preparing chipsalliance.org:cores:SweRV_EH1:1.8 INFO: Downloading chipsalliance/Cores-SweRV from github INFO: Preparing fusesoc:utils:generators:0.1.5 INFO: Downloading fusesoc/fusesoc-generators from github INFO:...

mhamzaali