UHDM-integration-tests

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Asking for help with `yosys` synthesis of a RISC-V CPU written in SystemVerilog

4

I wrote a [RISC-V processor](https://github.com/jeras/rp32) in heavy SystemVerilog with a lot of: * arrays, `struct`ures, `union`s, `typedef`s, `enumeration`s, custom type `parameter`s, ... * assignment patterns, * don't care conditions and...

jeras

rkapuscik

Add ImportStructTypeOfPortWithFieldOfTheSameNameAsRangeParameter test

3

RRozak

The values assigned to ports `a` are different when the vanilla verilator is used instead of uhdm-verilator. That situation is in the tests: unary_op_minus unary_op_not_log unary_op_plus

RRozak

We need to check status of every file (Is it parsable by Surelog? Is it parsable by Yosys? Is vivado is generating bitstream? Is bitstream works on HW?). This issue...

kamilrakoczy

RRozak

RRozak

Add PatternReplicationPassedToPort test

1

RRozak

Because of parameter substitution, this test is similar to PatternReplicationPassedToPort test from https://github.com/chipsalliance/UHDM-integration-tests/pull/632. The error is exactly the same: ``` %Error-UNSUPPORTED: /home/rrozak/Documents/verilator/uhdm-integration/tests/ReplicationOfAssignmentPattern//top.sv:3:18: Unsupported/Illegal: Assignment pattern member not underneath a supported...

RRozak

Add PatternWithEnumTypeInNestedModule

3

RRozak