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Published 20 hours ago • verified publisher icon chipsalliance

Add PatternTypeInNestedModule test

Open RRozak opened this issue 3 years ago • 3 comments

RRozak avatar Sep 06 '21 14:09 RRozak

Blocked by https://github.com/chipsalliance/Surelog/issues/1808

RRozak avatar Sep 06 '21 15:09 RRozak

Uhdm verilator prints 28, but the original prints 24

RRozak avatar Sep 17 '21 14:09 RRozak

It looks like that problem is on verilator side. The typespec of parameter is correct, but verilator looks only on the name of the type and assumes that it is the one from current scope.

RRozak avatar Nov 10 '21 09:11 RRozak