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Published 20 hours ago • verified publisher icon chipsalliance

Adding FPU with EH2

Open zeeshanrafique23 opened this issue 2 years ago • 6 comments

Hi @jrahmeh, I am trying to add a floating point unit with EH2 as a out of pipe just like division is implemented. Just want to have some guidance or points to keep in mind. I have generated the equations for for Single Precision i.e "F-extension" and now following the implemented of DIV unit to replicate that for FPU. Thanks,

zeeshanrafique23 avatar May 07 '22 06:05 zeeshanrafique23

Hi Zeeshan,

You would need to turn on the f bit in the MISA CSR. You would need to make the VS bits writeable in the MSTATUS CSR and set those bits to a non zero value. You would need to implement the FFLAGS, FRM, and FCSR CSRs.

Joe

On Sat, May 7, 2022, 1:03 AM Zeeshan Rafique @.***> wrote:

Hi @jrahmeh https://github.com/jrahmeh, I am trying to add a floating point unit with EH2 as a out of pipe just like division is implemented. Just want to have some guidance or points to keep in mind. I have generated the equations for for Single Precision i.e "F-extension" and now following the implemented of DIV unit to replicate that for FPU. Thanks,

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jrahmeh avatar May 09 '22 18:05 jrahmeh

Hi Joseph, Thanks for your valuable input I will keep these in mind during implementation.

zeeshanrafique23 avatar May 10 '22 04:05 zeeshanrafique23

Hi @jrahmeh, Where can I get the input file of predecoder for espresso, I also need to change the predecoder to allow F instructions. https://github.com/chipsalliance/Cores-SweRV-EH2/blob/a95fdb81ea6dc19239cfe2953ef00710a6f1cf2a/design/ifu/eh2_ifu_aln_ctl.sv#L1144

zeeshanrafique23 avatar Jun 02 '22 12:06 zeeshanrafique23

Hi Zeeshan,

You will find the input files of predecoder in design/dec/decode and design/dec/cdecode (cdecode is for compressed instructions).

Joe

jrahmeh avatar Jun 03 '22 15:06 jrahmeh

Hi @jrahmeh Thanks, I had used the decoder file when I was modifying the eh2_dec_dec_ctl module. I don't think that the decoder or cdecode file will also work for the predecoder as we want predecoder as an output, but the decoder file doesn't have. https://github.com/chipsalliance/Cores-SweRV-EH2/blob/a95fdb81ea6dc19239cfe2953ef00710a6f1cf2a/design/dec/decode#L342

zeeshanrafique23 avatar Jun 03 '22 20:06 zeeshanrafique23

Hi @zeeshanrafique23 you need to change the .type from fr to fd in coredecode.e file and rerun this command

espresso -Dso -oeqntott coredecode.e | addassign -pre out.  > equations

then do a copy/paste of out.alu, out.mul, out.i0_only and change it to predecode. in eh2_ifu_aln_ctl.sv

you need to do the same process for legal_equations

try doing this without your extension first and do a diff to compare

Vignajeth

vignajeth avatar Jun 07 '22 14:06 vignajeth