chenqian13

@JeanRochCoulon Thanks! @sjthales Hi! Could you please share your research on the maximum frequency that CVA6 can reach on FPGA？

@demofpga After I changed CLK_OUT1=100MHz, I updated cv64a6.dts under fpga/src/bootrom and regenerated bootrom_64.sv. Vivado did not report any errors. Additionally, I have updated cv64a6_genesysII.dts under cva6-sdk/uboot/arch/riscv/dts/ and regenerated the Linux...

@demofpga Can you show the details of the error reported by Vivado？

Hi! @jquevremont No, I'm using https://github.com/openhwgroup/cva6-sdk on xcku5p board. I added an axi master and axi slave in the design. I added the axi-slave device information (as shown in the...

@jquevremont OK, thank you for your quick reply！ I would greatly appreciate it if anyone else could continue to offer help or suggestions!

Hi! @jquevremont I followed the README in the "meta-cva6-yocto" repository and finally generated the content shown in the figure. Then I executed the following command: gunzip -c build/tmp-glibc/deploy/images/cv64a6-genesys2/core-image-minimal-cv64a6-genesys2.wic.gz | sudo...